Digital circuits commonly use a consistent logic level for internal signals. However, the logic level can vary from system to system and even within various subsystem circuits within the same system. A level shifter can be used to connect a digital circuit using one logic level to a digital circuit using another logic level. Multiple level shifters can be used, such as one in each system, where bidirectional shifting is required. A driver, for example, can convert from internal logic levels to levels that are compatible with standard interface line levels. A line receiver, for example, can converts from interface levels to internal voltage levels. Examples of standard interface levels include the transistor to transistor logic (TTL) or complimentary metal oxide semiconductor (CMOS) logic levels commonly found within integrated circuits. Within a digital system, such as a digital communication system, internal voltage levels can be referred to as logic levels, while external voltage levels can be referred to as line levels.
Digital circuits generally operate based on the logic signals having logical transitions from one level to another level, for example, according to a specified time period for synchronous digital circuits. When a level shifter is required, it is often the case that the timing of the original signal transitions is distorted. For modern high-speed digital receivers and related phase locked loop (PLL) circuits stringent duty-cycle distortion requirements are present for level shifters since duty cycle or bit period distortion in a high speed digital receiver directly affects the jitter budget of CDR.
While simple level shifters are available in the prior art that accurately and adequately translate levels associated with an input logic signal, such circuits have disadvantages in that they can distort the time domain characteristic of the signal, such as the duty-cycle, due to unmatched rise/fall transitions that do not correspond precisely enough with the timing characteristics of the original signal to be suitable for high speed digital communication applications. Such lack of matching or correspondence can lead disadvantageously to jitter, data errors, and the like.